The present invention relates to an analog-to-digital converter, a semiconductor device, and a voltage signal generating method, for example, an analog-to-digital converter including a micro voltage generating circuit, a semiconductor device including such an analog-to-digital converter, and a voltage signal generating method in the micro voltage generating circuit.
Japanese Patent No. 4763644 (hereinafter, Patent Document 1) discloses a dithering circuit for use in correcting quantization errors in a ΔΣ analog-to-digital converter (ADC: Analog to Digital Converter). The dithering circuit disclosed in Patent Document 1 includes a dither generation circuit for generating a plurality of complementary signal pairs, and a dither injection circuit for generating a plurality of dither signals from the plurality of complementary signal pairs and adding the generated dither signals to an analog input signal. The dither injection circuit has a capacitance provided for each of a plurality of complementary signal pairs. The dither generation circuit controls the switch of the dither injection circuit, and the dither injection circuit inputs the selected capacitance as a dither to the ΔΣADC. At this time, the dither generating circuit selects a capacitor to be used in accordance with the dither frequency. The capacitance of the dither injection circuit is sufficiently smaller than the sampling capacitance used for sampling the analog input signal, and is, for example, 1/10 or less of the sampling capacitance.